Some semiconductor technologies include a vertical power device such as a power DMOS (double-diffused MOS) and at least one logic device well in which one or more logic devices are disposed. When the power device is reverse biased and the logic device well is at the negative substrate potential, most of the current flows through the power device and into the semiconductor substrate to provide a useful reverse current capability. However, a percentage of this minority carrier current flows out of the power device and into the logic device well through a lateral parasitic bipolar transistor. This current generates undesirable potential drops within the logic well and can trigger further parasitic devices, disrupting proper functionality of the logic device(s) disposed in the logic device well. It is desirable to more effectively suppress the lateral flow of minority carriers toward the logic device well in order to ensure proper operation of the logic devices when the power device is reverse biased.